1. Technical Field
The present invention relates to a measurement apparatus and a measurement method for measures a signal under measurement, a test apparatus that tests a device under test, an electronic device, a program used by the measurement apparatus, and a recording medium storing thereon the program. More specifically, the present invention relates to a measurement apparatus that measures jitter in a signal under measurement output by a device under test.
2. Related Art
A known test of an electronic device involves measuring jitter in a signal under measurement output by the electronic device such as a semiconductor circuit. For example, jitter of such a signal under measurement is measured by a time interval analyzer, an oscilloscope, or the like by inputting the signal under measurement thereto. The time interval analyzer or the like allows such jitter to be calculated by measuring phase errors of edges of the signal under measurement.
Another known method for testing the electronic device is a function test for judging whether or not a pattern of a signal under measurement output by an electronic device matches a pattern of expected logic values. In this test, a test apparatus detects or converts a data pattern of the signal under measurement by comparing a voltage value of the signal under measurement output by the electronic device with a reference voltage when a predetermined test pattern is applied to the electronic device. The test apparatus then judges whether or not the data pattern matches the expected pattern.
It is therefore necessary to prepare the apparatus for measuring jitter and the apparatus for testing function in order to carry out the jitter test in addition to function tests as described above. Therefore, it has been costly to carry out the jitter test.
The apparatus for testing function compares the voltage value of the signal under measurement with the reference voltage at a preset timing. Therefore, it can detect the edges of the signal under measurement by shifting the strobe timing. The apparatus for testing function gives timing information each time the logic value of the signal under measurement transitions. It is then possible to measure the jitter by utilizing this capability, i.e., by using the apparatus for performing function testing.
However, the conventional apparatus for function testing is what sets sampling timing in a test rate synchronized with a period of the signal under measurement. Therefore, it is necessary to set a phase of the sampling timing for each test rate in order to gradually shift the relative phase of the sampling timing with respect to the signal under measurement within each test rate.
Thus it takes undesirably long test time to perform the jitter test by stepping the strobe timings. Furthermore, the measurement accuracy is unsuitable for the test because the timing is shifted according to the relative phase. It is therefore the objective of an aspect of the invention to determine a sampling timing that enables efficient and accurate measurement of jitter of the signal under measurement when an apparatus for function testing is used to sample the signal under measurement.
Since no method for determining this sampling timing is known, it is impossible to determine how measurement data should be processed to efficiently and accurately measure a characteristic of the signal under measurement, such as jitter, when measurement data is acquired that includes information concerning the jitter of the signal under measurement.
A case in which the length of the acquired data is not an integer multiple of a period of the signal under measurement is also considered. Furthermore, when a Fourier transform is performed to process the measurement data in the frequency domain, performing the Fourier transform by multiplying the measurement data by a window function is considered. However, since this amplitude of this measurement data is modulated by the window function, an error arises when extracting the jitter from the measurement data.
For coherent sampling, a reference signal is usually supplied to the device under test to cause the device under test to output a logic sequence being coherent with the applied reference signal. Therefore, the signal integrity of the logic sequence or signal output by the device under test is mainly determined by the limited signal integrity of the reference signal which the test apparatus generates, so that the performance limits of the device under test cannot be fully tested.
An aspect of the present invention aims to determine how to efficiently and accurately obtain a characteristic of the signal under measurement, such as jitter, from the measurement data of the signal under measurement. A further aim is to provide an apparatus that can perform non-coherent sampling to supply the device under test with a reference signal having high signal quality from an external oscillator, thereby testing the performance limits of the device under test.
When using an oscilloscope to measure the jitter, an amplitude noise component is included in the input signal under measurement, along with a timing noise component. This amplitude noise component makes it difficult to accurately measure only the timing noise of the signal under measurement. An aspect of the present invention makes clear that the timing noise of the signal under measurement can be accurately measured by using a voltage comparator disposed in an apparatus performing the functional test to remove the effect of the amplitude noise component from the signal under measurement. It is further shown that the state of the signal under measurement can be sampled using the voltage comparator, where “the state” refers to whether the logic value of the signal under measurement is the expected logic value.
It is also shown that a variety of measurements can be performed by using an apparatus for testing functionality provided with a plurality of measurement pins. For example, deterministic skew or random skew between a plurality of signals under measurement can be measured accurately and efficiently.
US Patent Application Publication No. 2005/0069031 (referred to hereinafter as “Patent Document 1”) discloses a technique for calculating the probability density function of jitter in the signal under measurement by means of undersamplng.
However, the invention disclosed in Patent Document 1 aims to detect jitter for only one edge type, as described in paragraph 0131 as “jitter for only one EDGE type is measured and the other edge is ignored.” Accordingly, it has a disadvantage that jitter for the other edge type cannot be measured. Additionally, since a method of measuring a cumulative density function is employed, it is necessary to perform pattern matching and also necessary to implement a state machine. For example, in order to detect a “01” bit pattern (a leading edge), it is necessary to implement the state machine capable of comparing two bit patterns. Moreover, the invention disclosed in Patent Document 1 cannot measure jitter in the time domain or the frequency domain.
For example, in order to measure jitter for the leading edge, it is necessary to check bits adjacent to each other to detect the “01” pattern as described in paragraph 0131 of Patent Document 1. First, a beat frequency signal Q is fed into a shift register having a 2J-bit width in a general purpose circuit shown in FIG. 9 of Patent Document 1 in accordance with sampling frequency fs. At this time, when the bit pattern is “01”, “1” is fed into the shift register as described in paragraph 0076 of Patent Document 1.
Next, a state machine 110 shown in FIG. 9 and FIG. 8B of Patent Document 1 uses a counter 132 to continuously count the number of bits having the value “1” (corresponding to “01”) which are continuously inputted (=state 2). When a predetermined number of “1” bits are continuously inputted, the carry Cout of the counter 132 is output to a counter 134 and a middle of a rising edge state 3 is recognized. Furthermore, when the counter 134 outputs the carry Cout to a counter 136, the discrete value of the counter 136 at a bin position in a cumulative density function CDF is increased. When the value of the counter 132 is equal to the value of the counter 136, the discrete value of a counter 138 at the bin position in the cumulative density function CDF is increased by 1. In this way, the cumulative density function CDF is measured as described in paragraph 0102 of Patent Document 1.
As described above, the invention disclosed in the Patent Document 1 is not suitable for a test apparatus that tests an electronic device. This is because a method capable of measuring jitter without limiting the edge type is desired for a test apparatus. For example, jitter appears as a plurality of impulses being adjacent to each other in FIG. 34C of the present specification.
Moreover, it is desired that jitter can be measured in both the time domain and frequency domain in addition to the probability density function (PDF). Finally, in order to perform a jitter test without changing the configuration of the current test apparatus, it is necessary to measure by comparing 1 bit of the sample values with 1 bit of the expected value without using pattern matching, which requires the state machine as mentioned above.
Moreover, paragraph 0129 explains that the jitter can be analyzed using a memory and a computer for the test apparatus. However, Patent Document 1 does not disclose how to analyze the jitter.
In US Patent Application Publication No. 2005/0243950 (referred to hereinafter as “Patent Document 2”), a method is disclosed for analyzing the spectrum of an error signal using critical sampling in a bit error rate measurement system. As shown in FIG. 2 of Patent Document 2, for each bit time interval a single sample point is sampled. That is, two points per period are sampled, so that the sampling is referred to as the critical sampling.
Patent Document 2 emphasizes providing the method for measuring the jitter spectrum. However, it has an essential drawback that in order to obtain the jitter value from the measurement value, it always requires the calibration measurement of a clock signal being modulated by the calibration signal, because of critical sampling. It is therefore impossible to measure the signal level accurately using critical sampling. Since jitter value can be viewed as the noise component in the signal-to-noise ratio, it is extremely important to measure the signal level to define and measure the signal-to-noise ratio required for jitter measurements.
It should be noted that an error signal is the result of comparing the expected data with the input logic data. Therefore, in order to efficiently observe the error signal by the technique disclosed in Patent Document 2, the time offset of a sampling timing has to be adjusted such that the bit-value transitions can be critically sampled at the adjusted timing point.
Conventional measuring methods, however, do not judge whether the detected transition point is a rising edge or a falling edge. Therefore, there are problematic cases where a falling edge of the signal under measurement is mistakenly detected as a rising edge during a test in which the rising edge is supposed to be detected to calculate the jitter amount of the detected edge.
Along with the increasing speed of devices in recent years, the pulse widths of signals under measurement have been becoming smaller. Therefore, even if a plurality of strobes are generated in the vicinity of the rising edge to detect the rising edge, the falling edge is also undesirably detected by the plurality of strobes. This causes a problem that two transition points are detected in the same period of the signal under measurement.
As described above, it is difficult for conventional measuring methods to detect whether a target edge is a rising edge or a falling edge. The inability to distinguish the edge type causes an error in the measured value of the jitter, so that the device under test cannot be accurately tested.